Conventional graphics processing pipelines include a vertex shader, hull shader, tessellation unit, domain shader, a geometry shader, and a pixel shader that each process graphics geometry and generate attributes. The attributes generated by the vertex shader, processed by a hull shader and passed to the tessellation unit that produces a primitive topology and then to the domain shader. Dedicated first-in first-out (FIFO) buffer circuits may be coupled between the vertex shader and tessellation unit, between the tessellation unit and the domain shader, between the domain shader and the geometry shader, and between the geometry shader and the pixel shader to accommodate different processing throughputs. However, the number of entries in the FIFO buffer circuits is limited.
The domain shader computes per-vertex attributes that are output to the pixel shader, e.g., position, lighting, texture coordinates, and color. Modern graphics processing pipelines may be configured to generate as many as 128 different attributes, so the amount of data that is passed between the different shaders for each vertex has increased compared with conventional graphics processing pipelines. The per-vertex attributes are output by the domain shader to the geometry shader, which may subdivide primitives that are defined by the vertices, thereby generating additional vertices and associated attributes that are output to a rasterizer. The rasterizer determines pixel coverage and outputs the per-vertex attributes to the pixel shader that are needed to determine a color for each pixel.
As graphics processing capabilities have improved, the size of the primitives has decreased, so that, in some cases, each primitive may only cover a single pixel. The amount of attribute data that is generated and passed through the graphics processing pipeline to produce each pixel of an image has increased significantly compared with traditional graphics processing. Consequently, the capacity of the FIFO buffer circuits may be exceeded, resulting in a reduction in processing throughput and decreased performance. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.